1. Technical Field
The present disclosure relates to a solid-state imaging device.
2. Description of the Related Art
Recently, as well as a CCD (Charge Coupled Device) type sensor (hereinafter referred to as a “CCD sensor”) which has predominated in image sensors, a MOS type image sensor (hereinafter referred to as a “MOS sensor”) utilizing a standard process used for a logic LSI has widely been on the market. Different from a CCD sensor, a MOS sensor has characteristics such that various analog circuits and digital circuits can be integrated on a substrate on which an imaging region is formed.
Further, a CCD sensor cannot obtain a digital output until an independent chip having an A/D conversion function, such as an analog front-end processor (hereinafter referred to as AFE) specializing in an analog signal amplification function and an A/D conversion function or a digital signal processor (hereinafter referred to as DSP) having a function of AFE, is connected to the imaging region. On the other hand, a MOS sensor in which an imaging region and an A/D conversion circuit are integrated on the same chip has been commercialized.
A lot of architectures have been proposed for an A/D conversion circuit mounted to a MOS sensor. At present, an image sensor using column A/D conversion for performing simultaneous parallel A/D conversion to image data for one line has predominated.
A column A/D conversion circuit includes a latch circuit and a driver circuit provided for each pixel (each column). The latch circuit temporarily holds pixel data obtained through A/D conversion. The driver circuit outputs this pixel data to a pair of read bit lines
A column scanning unit sequentially activates a plurality of driver circuits, thereby outputting a signal corresponding to the pixel data to the pair of read bit lines. A sense amplifier amplifies the signal output to the pair of read bit lines. A flip-flop holds this signal.
On the other hand, Unexamined Japanese Patent Publication No. 2000-207886 proposes a configuration of a data transfer circuit illustrated in FIG. 17.
This data transfer circuit includes a plurality of sub memory cell blocks 6. Each memory cell block 6 includes memory cells MC11, MC12, and MC1m which include a driver and a latch circuit for driving bit lines BL1 and XBL1, and a sub-read circuit.
With this configuration, the parasitic resistance and parasitic capacitance of the bit lines BL1 and XBL1 driven by the drivers can be reduced, whereby the data of memory cells MC11, MC12, and MC1m can be transmitted to the sub-read circuit at high speed.